The Faculty of Engineering at The University of Western Ontario (UWO) is committed to develop a strong Microsystems-DSP research and education program. The Microsystems-DSP group has been established very recently within the Department of Electrical and Computer Engineering at the University of Western Ontario. Most of the group members are emerging highly qualified junior researchers, recently recruited by the Faculty of Engineering. The Microsystems-DSP area at UWO is fast growing and continuously being strengthened by addition of faculty members and by acquisition of new laboratory facilities for innovative research and training of highly qualified engineers.
The Microsystems challenges are a result of the scaling of CMOS technology into nanometers dimensions. This is due to the physical limitations of the Silicon MOSFET transistors necessitating development work at both the device structures and circuit techniques levels. The group has expertise and strength in the semiconductor and photonic devices, medical image and digital signal processing, and in the development of ASIC and FPGA-algorithms and implementation techniques for various Microsystems applications. The detailed research activities by this group are described below.
AREAS OF STRENGTH
VLSI at System Level
The group is working on numerous VLSI applications, such as digital signal processing, cryptography, telecommunication, medical image processing and digital control systems. The research is also concerned with developing algorithms, architectures, and efficient application specific integrated circuit (ASIC) and field programmable gate array (FPGA) design methodologies of high-speed and low-power VLSI digital systems for above applications.
VLSI Circuit Design
The research projects are concerned with developing high-speed and low-power VLSI circuits for very-deep submicron and nanoscale technologies (beyond the 90nm node). Novel circuit techniques are also being developed to reduce leakage current with better noise immunity. Circuit-level design of high-speed digital circuits using SiGe-based BiCMOS logic family is being explored. Cadence tools, provided by CMC, are being used for the design and simulation (including chip layout). The fabrication of the designed VLSI chips is possible through Canadian Microelectronic Corporation. The computing facilities are located in a new VLSI laboratory.
VLSI Device Design and Simulation
Research work on emerging Si devices is being conducted. This is critical to sustain the growth and performance of CMOS-based digital circuits. Various structures of the scaled MOSFET transistor is being simulated and designed using 2D device simulators. This research work also involves the simulation and study of the complex optical modes in photonic crystal devices to enhance and optimize their optical output. The current photonic crystal light emitters suffer from low injection efficiencies and light output. Different emitter configurations are being studied to increase the efficiencies and enhance the modulation speeds of individual devices. Integrated photonic circuit design and simulations, to include both active and passive devices on the same substrate, will also be explored.
VLSI Nanoelectronics and Photonic devices
Nanoscale devices such as carbon nanotube, quantum-dot cellular automata (QCA), and single electron transistor (SET) are being studied. Recently, a powder-based separation technique for the carbon nanotube circuit designs has been proposed. These techniques will be very useful for the establishment of the next-generation of integrated circuits. Furthermore, an efficient majority-gate-based design technique was proposed for the QCA designs. The proposed technique will significantly reduce the complexity of the designs of the nanoscale QCA circuits, while providing a similar speed. Photonic devices research focuses on the design and fabrication of photonic crystal active light sources, detectors and passive single- and multi-channelled devices with the aim of eventually integrating them monolithically to realize photonic crystal circuits. Developing these devices involves extensive nanofabrication techniques and utilizes specialized high-speed optical characterization equipment. These densely integrated photonic chips will further be customized for high speed optical communication applications and very sensitive bio-photonic sensors.
VLSI Field-Programmable-Gate-Array (FPGA)
FPGA algorithms and implementations for control, medical image processor, and telecommunication and DSP processor are being studied. Several projects in progress include Low-power and high-speed digital design; implementation for DSP processors and MPEG codec; Algorithms and implementation of different coding schemes in computer networks and wireless telecommunication systems; Algorithms and implementation for the digital feedback; Algorithms and implementation for the RSA encryption system; implementation of digital image processing algorithms.
Speech and Audio Signal Processing (DSP)
This research involves developing speech and audio processing algorithms for Audiology and Speech Language Pathology applications. Current projects include adaptive modeling of digital hearing aids using sub-band adaptive structures; objective and subjective measurements of hearing aid sound quality and noise reduction performance; interaction between the speech coders used in modern communication systems and the persons with communication disabilities; development of a multi-channel psychoacoustic testing system; evaluation of directional performance of hearing aids in a hemi-anechoic chamber; advanced acoustic, electroglottographic, and aerodynamic signal analysis for the diagnosis and treatment monitoring for different voice disorders.
Biomedical Signal Processing (DSP)
This is a cross-disciplinary emerging area of research that aims to extract and process information from biomedical signals. Projects that are currently underway and/or are in the planning stages include : development of DSP algorithms for the analysis of EEG signals; design of algorithms for EEG-based monitoring of patients with head trauma; development of noise reduction algorithms for fMRI data acquisition; advanced spectral analysis algorithms for neural spike pattern recognition.
The research carried out within this group is mainly concentrated in applications of VLSI technology to implement DSP algorithms for various applications. At present time, it includes: Audiology and Speech Language Pathology, real-time heart sound and EEG signal analysis, medical image processing, and analysis and the design of virtual environments for surgical procedures and training. The main objective of this group is to develop synergy between faculty members in VLSI hardware and DSP algorithms for novel applications.
- Dr. A. Dounavis
- Dr. J. Jiang
- Dr. H. Ladak
- Dr. V. Parsa
- Dr. A. Reyhani-Masoleh
- Dr. J. Sabarinathan
- Dr. S. Salisbury
- Dr. J. Samarabandu
- Dr. R. Sobot
The VLSI-DSP laboratories are located in the new Thompson Engineerin Building. The VLSI laboratory is being established and it has 8 PCs (provided by CMC) with Matlab and FPGA software for VLSI DSP prototype designs. More than 15 workstations are being used for teaching VLSI circuit design using Cadence tools (provided by CMC).
The DSP group has recently received a significant equipment donation from Texas Instruments Inc., Dallas, USA. The donated equipment includes fifteen DSP development boards based on the 225 MHz floating point TMS320C6713 chip, four Test and Evaluation Boards (TEBs) based on the C6701 and C6416 DSP chips, the Network and Video Development Kit (NVDK), and the complete version of the Code Composer Studio (CCS) integrated software development environment. The acquisition of the TI DSP hardware and software has paved the way to the creation of state-of-the-art DSP teaching and research laboratories.
COLLABORATIONS AND INDUSTRY LINKS
The VLSI-DSP group members have established collaborations with various research centres and universities. Some of the collaborators names are given below:
- VLSI research group at Northwestern University
- Nano research group at University of Calgary
- Chemical Engineering department
- Nanofabrication facility at UWO
- Physics department at UWO
- Robarts Research Institute
- Faculty of Health Sciences, UWO
- Biomedical Engineering, UWO
- School of Communication Sciences and Disorders
- National Centre for Audiology
- Ryerson University
- DSP factory Ltd., Waterloo
- Z. Abid, Mrinmoy Barua and A. Alma'aitah, "Design of a Transmission-Gate based CMOL Memory Array", accepted for publication, Micro & Nano Letters, IET publications, 2008.
- Z. Abid, H. El-Razouk and D. A. El-Dib, "Low power multipliers based on new hybrid full adders", accepted for publication, Microelectronics Journal, 2008.
- Z. Abid and Wei Wang, "Countermeasures for Hardware Fault Attack in Multi-Prime RSA Cryptosystems", International Journal of Network Security, Vol.6, No.2, pp.190-200, Mar. 2008.
- Z. Abid and H. El-Razouk, "Defect Tolerant Voter Designs Based on Transistors Redundancy", Journal of Low Power Electronics, American Scientific Publishers, V.2, N.3, pp. 456-463, Dec. 2006.
- I. Erdin, A. Dounavis, R. Achar and M. Nakhla, "A SPICE Model for Incident Field Coupling to Lossy Multiconductor Transmission Lines" , IEEE Transactions Electromagnetic Compatibility , vol. 43, no 4, pp. 485-494, Nov. 2001.
- A. Dounavis, R. Achar and M. Nakhla, "Addressing Transient Errors in Passive Macromodels of Distributed Transmission Line Networks, IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 12, pp. 2759-2768, Dec. 2002.
- I. M. Elfadel, H. M. Huang, A. E. Ruehli, A. Dounavis and M. Nakhla, "A Comparative Study of Two Transient Analysis Algorithms for Lossy Transmission Lines with Frequency-Dependent Data", IEEE Transactions on Advanced Packaging, vol. 25, no. 2, pp 143-153, May 2002.
- A. Dounavis, R. Achar and M. Nakhla, "Efficient Sensitivity Analysis of Lossy Multiconductor Transmission Lines with Nonlinear Terminations" , IEEE Transactions on Microwave Theory and Techniques, vol. 49, no. 12, pp. 2292-2299, Dec 2001.
- Jiang, J. and Zhang, Y. "A novel variable-length sliding window blockwise least-squares algorithm for on-line estimation of time-varying parameters," International Journal of Adaptive and Signal Processing, Vo. 18, pp. 505-521, 2004.
- Jiang, J. and Zhang, Y. "A revisit to block and recursive least squares for parameter estimation,"Journal of Computers and Electrical Engineering, 2004.
- Sejdic, E. and Jiang, J. "Comparative study of three time-frequency representations with applications to a novel correlation method," Proc. of International Conference on Acoustics, Speech, and Signal Processing, Montreal, May 17-21, 2004.
- Li, W. and Jiang, J. "Isolation of parametric faults in continuous-time multivariate systems: A sampled data-based approach," International Journal of Control, Vol. 20, pp. 173-187, 2004.
- Ladak HM, Dirckx JJJ, Decraemer WF, Funnell WRJ. Response of the cat eardrum to static pressures: Mobile versus immobile malleus. J Acoust Soc Am; 2004; in press.
- Ladak HM, Wang Y, Downey DB, Fenster A. Testing and optimization of a semi-automatic prostate boundary segmentation algorithm using virtual operators. Med Phys; 2003; 30: 1637-1647.
- Ladak HM, Mao F, Wang Y, Downey DB, Steinman DA, Fenster A. Prostate boundary segmentation from 2D ultrasound images. Med Phys; 2000; 27: 1777-1788.
- Ladak HM, Decraemer WF, Dirckx JJJ, Funnell WRJ. Systematic errors in small deformations measured by use of shadow-moire topography. Appl Opt; 2000; 39: 3266-3275.
- Chen, G. and Parsa, V. Output-based speech quality evaluation by measuring perceptual spectral density distribution, IEE Electronics Letters, 40, 783-785, 2004.
- Parsa, V. and Jamieson, D.G. Interactions Between Speech Coders and Disordered Speech, Journal of Speech Communication, 40, 365-385, 2003.
- Parsa, V. and Jamieson, D.G. Acoustic discrimination of pathological voice: Sustained vowels versus continuous speech, Journal of Speech, Language and Hearing Research, 44, 327-339, 2001.
- Parsa, V., Parker, P.A. and Scott, R.N. Adaptive stimulus artefact reduction in noncortical somatosensory evoked potential studies. IEEE Trans. on Biomedical Engineering, 45, 165-179, 1998.
- A. Reyhani-Masoleh and M. A. Hasan, "Low Complexity Word-Level Sequential Normal Basis Multipliers," IEEE Transactions on Computers, pp 98-110, Vol. 54, No. 2, February 2005.
- A. Reyhani-Masoleh and M. A. Hasan, "Low Complexity Bit Parallel Polynomial Basis Multiplication over GF(2^m)," IEEE Transactions on Computers, pp 945-959, Vol. 53, No. 8, August 2004.
- A. Reyhani-Masoleh and M. A. Hasan, "Efficient Digit-Serial Normal Basis Multipliers over Binary Extension Fields," ACM Transactions on Embedded Computing Systems (TECS), Special Issue on Embedded Systems and Security, pp 575-592, Volume 3, Issue 3, August 2004.
- A. Reyhani-Masoleh and M. A. Hasan, "Towards Fault Tolerant Cryptographic Computations over Finite Fields," ACM Transactions on Embedded Computing Systems (TECS), Special Issue on Embedded Systems and Security, pp 593 - 613, Volume 3 , Issue 3, August 2004.
- A. Reyhani-Masoleh and M. A. Hasan, "Efficient Multiplication Beyond Optimal Normal Bases," IEEE Transactions on Computers, Special Issue on Cryptographic Hardware and Embedded Systems, pp 428-439 Vol. 52, No. 4, April 2003.
- J. Sabarinathan, P. Bhattacharya, P-C. Yu, S. Krishna, J. Cheng, D. G. Steel, An electrically injected InAs/GaAs quantum dot photonic crystal microcavity light emitting diode, Appl. Phys. Lett., vol. 81, no. 20, pp.3876-3878, November 2002.
- J. Sabarinathan, P. Bhattacharya, D. Zhu, B. Kochman, W. D. Zhou, P. C. Yu, Submicron three-dimensional infrared GaAs/AlxOy-based photonic crystal using single-step epitaxial growth, Appl. Phys. Lett., vol. 78, pp. 3024-3026, May 2001.
- P. Bhattacharya, J. Sabarinathan, W-D. Zhou, P-C. Yu, A. McGurn, Cavities of Crystal Light - Electrically Injected Photonic Crystal Microcavity Light Sources, (INVITED), IEEE Ckts. Dev. Mag., vol. 19, no. 2, pp. 25-33, March 2003.
- W. D. Zhou, J. Sabarinathan, P. Bhattacharya, B. Kochman, E. Berg, P.C. Yu, and S. Pang, Characteristics of a photonic bandgap single defect microcavity electroluminescent device, J. Quantum. Electron., vol. 37(9), pp. 1153-1160, September 2001.
- R. Sobot, S. Stapleton, M. Syrzycki, "A Fractional Delay ΣΔ Upconverter", IEE Electronics Letters, Volume 41, Issue 23, pp.15-16, November 2005.
- R. Sobot, S. Stapleton, M. Syrzycki, "Tunable Continuous Time Bandpass ΣΔ Modulators with Fractional Delays", IEEE Transactions on Circuits and Systems Part I: Regular Papers, (in print).
- R. Sobot, S. Stapleton, M. Syrzycki, "Tunable Center Frequency CT BP ΔΣ Modulators for Wireless Transceivers" , IEEE Vehicular Technology Conference 2004-Fall, Vol. 7, pp.4956-4960, Los Angeles, USA, September 26-29, 2004.